MOSFET Device Physics#

A few definitions:

\(V_{DS}\)

Voltage from drain to source.

\(V_{GS}\)

Voltage from gate to source.

Regimes of Operation#

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Fig. 1 Physical model of a transistor and its circuit representation.#

In this configuration, the transistor is off. The p-substrate is almost an insulator, and the transistor doesn’t conduct. There’s no current, because there’s nowhere for it to go!

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Fig. 2 The gate voltage is less than the drain voltage, and the transistor is off.#

The gate voltage is rising, repelling p-type carriers away from the channel.

In this situation, the electrons are still all attached to their atoms’ nucleus and are not moving. The negative ions are forming a depletion region; there are no free carriers, but the net charge of the region in the material is negative.

Since there are no holes or carriers to conduct electrons, the current is still zero.

doping

the introduction of impurities into a semiconductor crystal. It can leave open holes for electrons to fill in the crystal lattice, or have too many electrons to fill the valence shell. This means free carriers are introduced, but since the total number of protons and electrons are equal, it still leaves the material electrically neutral.

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Fig. 3 The gate voltage is greater than the drain voltage, the transistor is on, and current starts to flow.#

The gate voltage is now greater than the threshold voltage, and the electrons form a channel close to the gate. Free electrons can detach from their nucleus and flow. Current flow from the drain to the source is now non-zero.

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Fig. 4 3D view of a MOSFET with length and width dimensions labelled.#

Obviously, when \(V_{\text{GS}} \lt V_{\text{th}}\), \(I_D = 0\). When the gate voltage surpasses the threshold voltage, the current through the drain is given by

(1)#\[ I_D = \frac{1}{2} \mu c_{\text{ox}} \frac{W}{L} \left[ 2 (V_{\text{GS}} - V_{\text{th}}) V_{\text{DS}} - V_{DS}^2 \right] \]

where \(\mu\) is the electron mobility and \(c_{\text{ox}}\) is the gate oxide capacitance per unit area.

The larger \(L\) is, the smaller \(I_D\) is. Conversely, the wider \(W\) is, the greater \(I_D\) is.

../_images/mosfet_device_physics_9_0.png

Fig. 5 Current vs. drain voltage (assume \(V_{GS} \gt V_{th}\)).#

Note that in the above plot, the current is initially linear until the second term catches up. At \(V_{\text{DS}} = V_{\text{GS}} - V_{\text{th}}\), pinchoff occurs.

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Fig. 6 3D view of a MOSFET with length and width dimensions labelled.#

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Fig. 7 3D view of a MOSFET with length and width dimensions labelled.#

The channel is “pinched off.” This means a further increase of \(V_{\text{DS}}\) does not increase \(I_D\).

Note

So, is \(I_D = 0\)?

No; the super strong electric field in the pinched off region causes any electron entering that field to be swept away (an across).

../_images/mosfet_device_physics_16_0.png

Fig. 8 Current vs. drain voltage (assume \(V_{GS} \gt V_{th}\)).#

Analog designers mostly work in saturation, while digital designs usually operate in triode (and off).

Current Equations#

The current equations for triode and saturation are

(3)#\[ I_D = \frac{1}{2} \mu c_{\text{ox}} \frac{W}{L} \left[ 2 (V_{\text{GS}} - V_{\text{th}}) V_{\text{DS}} - V_{DS}^2 \right] \]

and

(3)#\[ I_D = \frac{1}{2} \mu c_{\text{ox}} \frac{W}{L} \left( V_{\text{GS}} - V_{\text{th}} \right)^2 \]

respectively.

../_images/mosfet_device_physics_19_0.png

Fig. 9 Current vs. drain voltage (assume \(V_{GS} \gt V_{th}\)).#

The lower \(V_{\text{GS}}\), the earlier the transition happens.

\(V_{\text{th}}\) doesn’t usually change; it’s typically around \(0.5 \text{V}\).

../_images/mosfet_device_physics_22_0.png

Fig. 10 Current vs. drain voltage (assume \(V_{GS} \gt V_{th}\)).#

The current resembles the I-V curve of a resistor when biased in this region.

In triode,

\[\begin{split} \frac{\partial I_D}{\partial V_{\text{DS}}} &= \frac{1}{2} \mu c_{\text{ox}} \frac{W}{L} \left[ 2 (V_{\text{GS}} - V_{\text{th}}) - 2 V_{\text{DS}} \right] \\ &\approxeq \mu c_{\text{ox}} \frac{W}{L} \left( V_{\text{GS}} - V_{\text{th}} \right) \end{split}\]

if \(V_{\text{GS}} - V_{\text{th}} \gg V_{\text{DS}}\), and the resistance is given by

\[ R = \left( \frac{\partial I_D}{\partial V_{\text{DS}}} \right)^{-1} \approxeq \frac{1}{\mu c_{\text{ox}} \frac{W}{L} \left( V_{\text{GS}} - V_{\text{th}} \right)} \]

because resistance is defined as the inverse of the slope of the IV characteristic curve.

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Fig. 11 A MOSFET in triode can be used as a voltage-controlled resistor.#

Transconductance#

transconductance

Transconductance is an expression of the performance of a field-effect transistor (FET). In general, the larger the transconductance figure for a device, the greater the gain (amplification) it is capable of delivering, when all other factors are held constant. For a FET, transconductance is the ratio of the change in drain current to the change in gate voltage over a defined, arbitrarily small interval on the drain-current-versus-gate-voltage curve. The unit is the siemens.

Transconductance in saturation is given by:

(4)#\[\begin{split} g_m &= \frac{\partial I_D}{\partial V_{\text{GS}}} = \frac{\partial \frac{1}{2} \mu c_{\text{ox}} \frac{W}{L} \left( V_{\text{GS}} - V_{\text{th}} \right)^2 }{\partial V_{\text{GS}}} \\ g_m &= \mu c_{\text{ox}} \frac{W}{L} \left( V_{\text{GS}} - V_{\text{th}} \right) \\ g_m &= \sqrt{2 \mu c_{\text{ox}} \frac{W}{L} I_D} \\ g_m &= \frac{2 I_D}{V_{\text{GS}} - V_{\text{th}}} \end{split}\]

\(g_m\) is the slope at some point \(V_{\text{GS}}\).

../_images/mosfet_device_physics_27_0.png

Fig. 12 \(g_m\) is the slope at some point \(V_{\text{GS}}\).#

Channel-length modulation#

Channel-length modulation (CLM) is a second order effect that doesn’t affect the IV curve as strongly. The channel length \(L\) becomes smaller as \(V_{\text{DS}}\) increases. As you increase \(V_{\text{DS}}\), the pinchout zone gets a bit smaller, increasing \(I_D\). Sometimes we ignore this effect.

../_images/mosfet_device_physics_31_0.png

Fig. 13 Current with and without channel-length modulation.#

The corresponding equation when in saturation is

(5)#\[ I_D = \frac{1}{2} \mu c_{\text{ox}} \frac{W}{L} \left( V_{\text{GS}} - V_{\text{th}} \right)^2 \left( 1 + \lambda V_{\text{DS}} \right) \]

and its slope is

\[\begin{split} \frac{\partial I_D}{\partial V_{\text{DS}}} &= \frac{1}{2} \mu c_{\text{ox}} \frac{W}{L} \left( V_{\text{GS}} - V_{\text{th}} \right)^2 \lambda \\ &= I_D \rvert_{\text{w/o CLM}} \times \lambda \end{split}\]

where \(\lambda\) is a process parameter that varies with transistor length.

The smaller the architecture, the more pronounced CLM effects will be. This is bad for analog design! If you want a smaller slope, make \(L\) bigger (or have a smaller current)!

../_images/mosfet_device_physics_33_0.png

Fig. 14 The per-channel-length early voltage.#

If \(V_E L \gg V_{\text{DS}}^{'}\):

\[ m = \frac{I_D^{'}}{V_E L + V_{\text{DS}}^{'}} \approxeq \frac{I_D^{'}}{V_E L} \]

and therefore

(6)#\[ \lambda \approxeq \frac{1}{V_E L} \]

Body effect#

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Subthreshold conduction#

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MOSFET capacitance#

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MOSFET as a varactor#

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